A memory testing apparatus for testing a writable/readable memory (hereinafter referred to as RAM) generally comprises a timing generator, a pattern generator, a waveform generator, a logical comparator and a failure analysis memory. As is well known, a RAM and a read only memory (hereinafter referred to as ROM) are often formed as a semiconductor integrated circuit element. In the following description, in order to facilitate understanding of the present invention, a case will be discussed in which a memory as constructed in the form of a semiconductor integrated circuit element (hereinafter referred to as IC memory) is tested by such memory testing apparatus, but it is to be noted that the memory testing apparatus can also test memories other than IC memories.
A pattern generator is operative, in response to a reference clock (operating clock) fed from the timing generator, to generate address pattern data, test pattern data, control signals and the like which are to be applied to an IC memory to be tested (memory under test), and also to generate expected value pattern data and the like which are to be supplied to the logical comparator.
An IC memory to be tested (commonly called MUT (memory under test)) is controlled in writing of a test pattern signal therein or reading of a test pattern signal therefrom by application of a control signal thereto. Specifically, when a writing control signal is applied to the IC memory under test, a test pattern signal is successively written in the IC memory under test at an address thereof specified by an address pattern signal, and when a reading control signal is applied to the IC memory under test, the test pattern signal previously written in the IC memory under test is successively read out thereof at an address specified by an address pattern signal.
A response output signal read out of the IC memory under test (hereinafter, also referred to simply as memory under test) is supplied to the logical comparator where it is logically compared with an expected value pattern data outputted from the pattern generator. If a result of the comparison indicates that there is an anti-coincidence or a mismatch therebetween, the logical comparator outputs a defective signal representing the anti-coincidence, namely, so-called failure data. Usually, as the failure data is outputted logical "1" which is a high logical level (logic H). By contrast, if a result of the comparison indicates that they coincide with each other, the logical comparator outputs a conforming or defectless signal representing the coincidence, namely, so-called pass data. Since the failure data is represented by logical "1", as the pass data is outputted logical "0" which is a low logical level (logic L). The failure data is fed to and stored in the failure analysis memory.
The failure analysis memory has the same operating rate or speed and storage capacity as those of the memory under test, and the same address pattern signal as that applied to the memory under test is applied to the failure analyses memory. In addition, the failure analysis memory is initialized prior to the start of a test. For example, when initialized, the failure analysis memory has data of logical "0s" written in all of the addresses thereof. Every time a failure data is generated from the logical comparator during a test of a memory under test, a failure data of logical "1" is written in the address of the failure analysis memory specified by the address pattern signal. That is, in a memory cell of the failure analysis memory having the same address as that of the failure memory cell of the memory under test is written the failure data (logical "1") indicating that failure memory cell of the memory under test.
Upon completion of one test cycle, a decision is rendered as to whether the memory under test is pass or failure in consideration of the number of failure data stored in the failure analysis memory, the locations where failure data occurred, and the like. By way of example, in case of utilizing the failure data stored in the failure analysis memory for purpose of relieving a defective memory cell of the memory under test, failure data read out of the failure analysis memory (information relating to the locations of defective memory cells of the memory under test) are totalled, and it is then determined based on the totalled failure data whether or not the locations of the detected failure memory cells can be relieved by relief means provided in the memory under test.
By contrast, when testing a ROM, test pattern data cannot be written in the ROM under test. Accordingly, there is provided a ROM expected value memory (constructed by a ROM) in which was previously stored the same data as the data which has previously written in the ROM under test, and the data read out of the ROM under test is logically compared with the expected value pattern data read out of the ROM expected value memory in the logical comparator which outputs a failure data in the event a result of the comparison indicates that there is an anti-coincidence or a mismatch therebetween.
FIG. 3 is a block diagram schematically showing the construction of a conventional memory testing apparatus provided with a ROM expected value memory. This memory testing apparatus is arranged to be capable of testing both a RAM and a ROM.
Referring to FIG. 3, the memory testing apparatus 100 comprises a timing generator 20 for generating a reference clock (operating clock) which controls the operation of various parts or components, a pattern generator 11 for outputting address pattern data, test pattern data, expected value pattern data and the like, an address waveform generator 21 for generating an address pattern signal having a real waveform corresponding to an input address pattern data, a data waveform generator 22 for generating a test pattern signal having a real waveform corresponding to an input test pattern data, a driver 23 for applying the address pattern signal of real waveform generated from the address waveform generator 21 to an IC memory under test 200, a driver 24 for applying the test pattern signal of real waveform generated from the data waveform generator 22 to the IC memory under test 200, an analog comparator 25 for determining whether or not a response output signal read out of the IC memory under test 200 in the form of logic level has a given voltage value, a logical comparator 26 for logically comparing data of the comparison result outputted from the analog comparator 25 with an expected value pattern data supplied from the pattern generator 11, and a failure analysis memory 27 for storing a failure data outputted from the logical comparator 26 each time both the data do not coincide with each other in the logical comparator, the failure data being stored in a memory cell of the failure analysis memory 27 at the address position specified by an address pattern data supplied from the pattern generator 11.
The pattern generator 11 comprises a controller 12 to which the reference clock is supplied from the timing generator 20 and which controls the timing generator 20, an address pattern generator 13 controlled by the controller 12 for generating address pattern data, a test pattern generator 14 controlled by the controller 12 for generating test pattern data, expected value pattern data and the like, a ROM expected value memory 16 for generating expected value pattern data for testing a ROM in a ROM testing mode in which ROMs are to be tested, a switching circuit 15 for supplying the test pattern data and the expected value pattern data generated from the test pattern generator 14 to the data waveform generator 22 and to the logical comparator 26 respectively in a RAM testing mode in which RAMs are to be tested as well as supplying the ROM testing expected value pattern data read out of the ROM expected value memory 16 to the logical comparator 26 in the ROM testing mode, a first delay circuit 18A for delaying the address pattern data outputted from the address pattern generator 13 by a given time interval D1, and a second delay circuit 18B for delaying the test pattern data outputted from the test pattern generator 14 by the same time interval D1.
Further, in the illustrated example, the arrangement is such that the operation of the data waveform generator 22 is inhibited in the ROM testing mode whereby only an address pattern signal is applied to the IC memory under test 200 (ROM).
As stated above, in order to test two kinds of memories, namely, a RAM and a ROM, heretofore, the ROM expected value memory 16 has been provided on the input side of the switching circuit 15 so that the switching circuit 15 can select either of the RAM testing test pattern data and expected value data generated from the test pattern generator 14 or the ROM testing expected value pattern data read out of the ROM expected value memory 16 to supply it to the data waveform generator 22 and the logical comparator 26.
Specifically, in the ROM testing mode, the address pattern data outputted from the address pattern generator 13 is applied to the ROM expected value memory 16 thereby to read the ROM testing expected value pattern data therefrom which is in turn outputted to the logical comparator 26 through the switching circuit 15.
To enable the memory testing apparatus to test a plurality of kinds of ROMs, the ROM expected value memory 16 is constructed by a RAM and the same data as that previously stored in a ROM under test has been written in this RAM. However, it should be understood that the ROM expected value memory 16 may be constructed by a ROM. The ROM expected value memory 16 involves a time lag or delay by nature between the time that the memory 16 is accessed and the time that the accessed data is read out thereof. Assuming that this time delay is represented by D1, unless the address pattern data supplied from the address pattern generator 13 to the address waveform generator 21 is delayed by the same time interval D1, the ROM testing expected value pattern data read out of the ROM expected value memory 16 and this address pattern data can not be fed in the same phase with each other to the logical comparator 26 and the address waveform generator 21.
In order to delay the address pattern data by the time interval D1, if the first delay circuit 18A having the time delay of D1 is inserted in a transmission path 17A for the address pattern data, it results in that the phase of a test pattern data supplied from the test pattern generator 14 to the data waveform generator 22 in the RAM testing mode differs from that of the address pattern data. Therefore, it becomes necessary to connect the second delay circuit 18B having the same time delay of D1 in a transmission path 17B for the test pattern data.
Thus, when the circuit arrangement shown in FIG. 3 is taken, the first delay circuit 18 and the second delay circuit 18B having the same time delay must be inserted in the transmission path 17A for the address pattern data and in the transmission path 17B for the test pattern data, respectively.
In addition, assuming that a delay time is represented by D2, which is a time interval from the time point that an address pattern data is inputted to the input terminal of the address waveform generator 21, followed by that a data is read from the IC memory under test 200 at the corresponding address and that the read data is fed to the logical comparator 26 through the analog comparator 25, and to the time point that a failure data is supplied to the input side of the failure analysis memory 27 (shown in FIG. 3 by a bold solid line with an arrow), an address pattern data directly applied from the address pattern generator 13 to the failure analysis memory 27 must be delayed by a time interval of D1+D2 in order to make the address pattern data in phase with the failure data applied to the failure analysis memory 27, where D1 represents the time delay caused by the transmission path 17A for the address pattern data
Accordingly, it is necessary to insert a third delay circuit 18C having a time delay of (D1+D2) in a transmission path from the address pattern generator 13 to the failure analysis memory 27, as shown in FIG. 3.
It is to be understood that when an address pattern signal is applied to the address waveform generator 21 to read data from the IC memory under test 200, the expected value pattern data from the test pattern generator 14 or the expected value pattern data from the ROM expected value memory 16, one of which is outputted from the switching circuit 15 to the logical comparator 26, is normally matched in the logical comparator 26 in its phase with the phase of a data read out of the IC memory under test 200 and inputted to the logical comparator 26, and accordingly, an associated delay circuit is not shown. Obviously, a delay circuit may be used to match the phase of the expected value pattern data with the phase of the data read out of the IC memory under test 200 and inputted to the logical comparator 26.
Thus it will be seen that in the conventional memory testing apparatus 100 provided with the ROM expected value memory 16, there is a need to provide the first delay circuit 18A, the second delay circuit 18B and the third delay circuit 18C. The setting of the time delay in each of these delay circuits requires a troublesome operation because their relative time delay must be accurately defined, resulting in a disadvantage that the circuit arrangement becomes complicated. In addition, even though the time delays have been set up once, there are cases that the time delays may be varied due to change in temperature, with the lapse of time and the like, and hence a disadvantage occurs that much time and labor are required in its maintenance.